Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 193
DMA_CUR_DEST_REG
0x100+N*0x40+0x14
DMA Channel Current Destination Register
(N=0~11)
DMA_BCNT_LEFT_REG
0x100+N*0x40+0x18
DMA Channel Byte Counter Left Register
(N=0~11)
DMA_PARA_REG
0x100+N*0x40+0x1C
DMA Channel Parameter Register
(N=0~11)
DMA_FDESC_ADDR_REG
0x100+N*0x40+0x2C
DMA Formar Descriptor Address Register
(N=0~11)
DMA_PKG_NUM_REG
0x100+N*0x40+0x30
DMA Package Number Register
(N=0~11)
4.11.4. DMA Register Description
4.11.4.1. DMA IRQ Enable Register0 (Default Value: 0x00000000)
Offset: 0x0000
Register Name: DMA_IRQ_EN_REG0
Bit
R/W
Default/Hex
Description
31
/
/
/
30
R/W
0x0
DMA7_QUEUE_IRQ_EN
DMA 7 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
29
R/W
0x0
DMA7_PKG_IRQ_EN
DMA 7 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
28
R/W
0x0
DMA7_HLAF_IRQ_EN
DMA 7 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.
27
/
/
/
26
R/W
0x0
DMA6_QUEUE_IRQ_EN
DMA 6 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
25
R/W
0x0
DMA6_PKG_IRQ_EN
DMA 6 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
24
R/W
0x0
DMA6_HLAF_IRQ_EN
DMA 6 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.
23
/
/
/
22
R/W
0x0
DMA5_QUEUE_IRQ_EN
DMA 5 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
21
R/W
0x0
DMA5_PKG_IRQ_EN
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