Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 194
DMA 5 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
20
R/W
0x0
DMA5_HLAF_IRQ_EN
DMA 5 Half package Transfer Interrupt Enable.
0: Disable, 1: Enable.
19
/
/
/
18
R/W
0x0
DMA4_QUEUE_IRQ_EN
DMA 4 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
17
R/W
0x0
DMA4_PKG_IRQ_EN
DMA 4 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
16
R/W
0x0
DMA4_HLAF_IRQ_EN
DMA 4 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.
15
/
/
/
14
R/W
0x0
DMA3_QUEUE_IRQ_EN
DMA 3 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
13
R/W
0x0
DMA3_PKG_IRQ_EN
DMA 3 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
12
R/W
0x0
DMA3_HLAF_IRQ_EN
DMA 3 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.
11
/
/
/
10
R/W
0x0
DMA2_QUEUE_IRQ_EN
DMA 2 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
9
R/W
0x0
DMA2_PKG_IRQ_EN
DMA 2 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
8
R/W
0x0
DMA2_HLAF_IRQ_EN
DMA 2 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.
7
/
/
/
6
R/W
0x0
DMA1_QUEUE_IRQ_EN
DMA 1 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
5
R/W
0x0
DMA1_PKG_IRQ_EN
DMA 1 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
4
R/W
0x0
DMA1_HLAF_IRQ_EN
DMA 1 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable.
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