Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 195
3
/
/
/
2
R/W
0x0
DMA0_QUEUE_IRQ_EN
DMA 0 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
1
R/W
0x0
DMA0_PKG_IRQ_EN
DMA 0 Package End Transfer Interrupt Enable.
0: Disable, 1: Enable.
0
R/W
0x0
DMA0_HLAF_IRQ_EN
DMA 0 Half Package Transfer Interrupt Enable.
0: Disable, 1: Enable
4.11.4.2. DMA IRQ Enable Register1 (Default Value: 0x00000000)
Offset: 0x0004
Register Name: DMA_IRQ_EN_REG1
Bit
R/W
Default/Hex
Description
31:15
/
/
/
14
R/W
0x0
DMA11_QUEUE_IRQ_EN
DMA 11 Queue End Transfer Interrupt Enable.
0: Disable, 1: Enable.
13
R/W
0x0
DMA11_PKG_IRQ_EN
DMA 11 Package End Transfer Interrupt Enable.
0: Disable
1: Enable
12
R/W
0x0
DMA11_HLAF_IRQ_EN
DMA 11 Half Package Transfer Interrupt Enable.
0: Disable
1: Enable
11
/
/
/
10
R/W
0x0
DMA10_QUEUE_IRQ_EN
DMA 10 Queue End Transfer Interrupt Enable.
0: Disable
1: Enable
9
R/W
0x0
DMA10_PKG_IRQ_EN
DMA 10 Package End Transfer Interrupt Enable.
0: Disable
1: Enable
8
R/W
0x0
DMA10_HLAF_IRQ_EN
DMA 10 Half Package Transfer Interrupt Enable.
0: Disable
1: Enable
7
/
/
/
6
R/W
0x0
DMA9_QUEUE_IRQ_EN
DMA 9 Queue End Transfer Interrupt Enable.
0: Disable
confidential