Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 196
1: Enable
5
R/W
0x0
DMA9_PKG_IRQ_EN
DMA 9 Package End Transfer Interrupt Enable.
0: Disable
1: Enable
4
R/W
0x0
DMA9_HLAF_IRQ_EN
DMA 9 Half package Transfer Interrupt Enable.
0: Disable
1: Enable
3
/
/
/
2
R/W
0x0
DMA8_QUEUE_IRQ_EN
DMA 8 Queue End Transfer Interrupt Enable.
0: Disable
1: Enable
1
R/W
0x0
DMA8_PKG_IRQ_EN
DMA 8 Package End Transfer Interrupt Enable.
0: Disable
1: Enable
0
R/W
0x0
DMA8_HLAF_IRQ_EN
DMA 8 Half Package Transfer Interrupt Enable.
0: Disable
1: Enable
4.11.4.3. DMA IRQ Pending Status Register0 (Default Value: 0x00000000)
Offset:0x10
Register Name: DMA_IRQ_PEND_REG0
Bit
R/W
Default/Hex
Description
31
/
/
/
30
R/W
0x0
DMA7_QUEUE_IRQ_PEND.
DMA 7 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
29
R/W
0x0
DMA7_PKG_IRQ_ PEND
DMA 7 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
28
R/W
0x0
DMA7_HLAF_IRQ_PEND.
DMA 7 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
27
/
/
/
26
R/W
0x0
DMA6_QUEUE_IRQ_PEND.
DMA 6 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
25
R/W
0x0
DMA6_PKG_IRQ_ PEND
DMA 6 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
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