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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 198
DMA 1 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
5
R/W
0x0
DMA1_PKG_IRQ_ PEND
DMA 1 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
4
R/W
0x0
DMA1_HLAF_IRQ_PEND.
DMA 1 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
3
/
/
/
2
R/W
0x0
DMA0_QUEUE_IRQ_PEND.
DMA 0 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
1
R/W
0x0
DMA0_PKG_IRQ_ PEND
DMA 0 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
0
R/W
0x0
DMA0_HLAF_IRQ_PEND.
DMA 0 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending.
4.11.4.4. DMA IRQ Pending Status Register1 (Default Value: 0x00000000)
Offset:0x14
Register Name: DMA_IRQ_PEND_REG1
Bit
R/W
Default/Hex
Description
31:15
/
/
/
14
R/W
0x0
DMA11_QUEUE_IRQ_PEND.
DMA 11 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
13
R/W
0x0
DMA11_PKG_IRQ_PEND
DMA 11 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect
1: Pending
12
R/W
0x0
DMA11_HLAF_IRQ_PEND.
DMA 11 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect
1: Pending
11
/
/
/
10
R/W
0x0
DMA10_QUEUE_IRQ_PEND.
DMA 10 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
9
R/W
0x0
DMA10_PKG_IRQ_ PEND
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