Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 199
DMA 10 Package End Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect
1: Pending
8
R/W
0x0
DMA10_HLAF_IRQ_PEND.
DMA 10 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear
it.
0: No effect
1: Pending
7
/
/
/
6
R/W
0x0
DMA9_QUEUE_IRQ_PEND.
DMA 9 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
5
R/W
0x0
DMA9_PKG_IRQ_ PEND
DMA 9 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
4
R/W
0x0
DMA9_HLAF_IRQ_PEND.
DMA 9 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
3
/
/
/
2
R/W
0x0
DMA8_QUEUE_IRQ_PEND.
DMA 8 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
1
R/W
0x0
DMA8_PKG_IRQ_ PEND
DMA 8 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
0
R/W
0x0
DMA8_HLAF_IRQ_PEND.
DMA 8 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it.
0: No effect
1: Pending
4.11.4.5. DMA Security Register (Default Value: 0x00000000)
Offset:0x20
Register Name: DMA_SECURE_REG
Bit
R/W
Default/Hex
Description
31:12
/
/
/
11
R/W
0x0
DMA11_SEC
DMA channel 11 security.
0: Secure,
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