Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 201
4.11.4.6. DMA Auto Gating Register (Default Value: 0x00000000)
Offset:0x28
Register Name: DMA_AUTO_GATE_REG
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2
R/W
0x0
DMA_MCLK_CIRCUIT.
DMA MCLK interface circuit auto gating bit.
0: Auto gating enable
1: Auto gating disable.
1
R/W
0x0
DMA_COMMON_CIRCUIT.
DMA common circuit auto gating bit.
0: Auto gating enable
1: Auto gating disable.
0
R/W
0x0
DMA_CHAN_CIRCUIT.
DMA channel circuit auto gating bit.
0: Auto gating enable
1: Auto gating disable.
4.11.4.7. DMA Status Register (Default Value: 0x00000000)
Offset:0x30
Register Name: DMA_STA_REG
Bit
R/W
Default/Hex
Description
31
/
/
/
30
RO
0x0
MBUS FIFO Status
0:Empty
1:Not Empty
29:12
/
/
/
11
RO
0x0
DMA11_STATUS
DMA Channel 11 Status.
0: Idle
1: Busy
10
RO
0x0
DMA10_STATUS
DMA Channel 10 Status.
0: Idle
1: Busy
9
RO
0x0
DMA9_STATUS
DMA Channel 9 Status.
0: Idle
1: Busy
8
RO
0x0
DMA8_STATUS
DMA Channel 8 Status.
0: Idle
1: Busy
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