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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 203
4.11.4.9. DMA Channel Pause Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x4(N=0~11)
Register Name: DMA_PAU_REG
Bit
R/W
Default/Hex
Description
31:1
/
/
/
0
R/W
0x0
DMA_PAUSE.
Pausing DMA Channel Transfer Data.
0: Resume Transferring,
1: Pause Transferring.
4.11.4.10. DMA Channel Descriptor Address Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x8(N=0~11)
Register Name: DMA_DESC_ADDR_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
DMA_DESC_ADDR
DMA Channel Descriptor Address.
The Descriptor Address must be word-aligned.
4.11.4.11. DMA Channel Configuration Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0xC(N=0~11)
Register Name: DMA_CFG_REG
Bit
R/W
Default/Hex
Description
31:27
/
/
/
26:25
RO
0x0
DMA_DEST_DATA_WIDTH.
DMA Destination Data Width.
00: 8-bit
01: 16-bit
10: 32-bit
11: 64-bit
24
/
/
/
23:22
RO
0x0
DMA_DEST_BST_LEN.
DMA Destination Burst Length.
00: 1
01: 4
10: 8
11: 16
21
RO
0x0
DMA_ADDR_MODE.
DMA Destination Address Mode
0x0: Linear Mode
0x1: IO Mode
20:16
RO
DMA_DEST_DRQ_TYPE.
DMA Destination DRQ Type
The details in DRQ Type and Port Corresponding Relation.
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