Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 204
15:11
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/
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10:9
RO
0x0
DMA_SRC_DATA_WIDTH.
DMA Source Data Width.
00: 8-bit
01: 16-bit
10: 32-bit
11: 64-bit
8
/
/
/
7:6
RO
0x0
DMA_SRC_BST_LEN.
DMA Source Burst Length.
00: 1
01: 4
10: 8
11: 16
5
RO
0x0
DMA_SRC_ADDR_MODE.
DMA Source Address Mode
0: Linear Mode
1: IO Mode
4:0
RO
0x0
DMA_SRC_DRQ_TYPE.
DMA Source DRQ Type
The details in DRQ Type and Port Corresponding Relation.
4.11.4.12. DMA Channel Current Source Address Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x10(N=0~11)
Register Name: DMA_CUR_SRC_REG
Bit
R/W
Default/Hex
Description
31:0
RO
0x0
DMA_CUR_SRC.
DMA Channel Current Source Address, read only.
4.11.4.13. DMA Channel Current Destination Address Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x14(N=0~11)
Register Name: DMA_CUR_DEST_REG
Bit
R/W
Default/Hex
Description
31:0
RO
0
DMA_CUR_DEST.
DMA Channel Current Destination Address, read only.
4.11.4.14. DMA Channel Byte Counter Left Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x18(N=0~11)
Register Name: DMA_BCNT_LEFT_REG
Bit
R/W
Default/Hex
Description
31:25
/
/
/
24:0
RO
0x0
DMA_BCNT_LEFT.
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