Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 205
DMA Channel Byte Counter Left, read only.
4.11.4.15. DMA Channel Parameter Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x1C(N=0~11)
Register Name: DMA_PARA_REG
Bit
R/W
Default/Hex
Description
31:8
/
/
/
7:0
RO
0x0
WAIT_CYC.
Wait Clock Cycles n.
4.11.4.16. DMA Former Descriptor Address Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x2C(N=0~11)
Register Name: DMA_FDESC_ADDR_REG
Bit
R/W
Default/Hex
Description
31:0
RO
0x0
DMA_FDESC_ADDR.
This register is used to storing the former value of DMA Channel Descriptor
Address Register.
4.11.4.17. DMA Package Number Register (Default Value: 0x00000000)
Offset: 0x100+N*0x40+0x30(N=0~11)
Register Name: DMA_PKG_NUM_REG
Bit
R/W
Default/Hex
Description
31:0
RO
0x0
DMA_PKG_NUM.
This register will record the number of packages which has been completed
in one transmission.
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