Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 217
1: Enable (It will notify user u by interrupt when Message Queue 3 is not
full.)
6
R/W
0x0
RECEPTION_MQ3_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 3 has
received a new message.)
5
R/W
0x0
TRANSMIT_MQ2_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 2 is not
full.)
4
R/W
0x0
RECEPTION_MQ2_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 2 has
received a new message.)
3
R/W
0x0
TRANSMIT_MQ1_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 1 is not
full.)
2
R/W
0x0
RECEPTION_MQ1_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 1 has
received a new message.)
1
R/W
0x0
TRANSMIT_MQ0_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 0 is not
full.)
0
R/W
0x0
RECEPTION_MQ0_IRQ_EN.
0: Disable
1: Enable (It will notify user u by interrupt when Message Queue 0 has
received a new message.)
4.13.5.4. MSGBox IRQ Status Register u(Default Value: 0x0000AAAA)
Offset:0x50+N*0x20 (N=0,1)
Register Name: MSGBOXU_IRQ_STATUS_REG
Bit
R/W
Default/Hex
Description
31:16
/
/
/
15
R/W
0x1
TRANSMIT_MQ7_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 7 is not
full. Set one to this bit will clear it.
14
R/W
0x0
RECEPTION_MQ7_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 7 has
received a new message. Set one to this bit will clear it.
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