Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 219
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 1 has
received a new message. Set one to this bit will clear it.
1
R/W
01
TRANSMIT_MQ0_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 0 is not
full. Set one to this bit will clear it.
0
R/W
0x0
RECEPTION_MQ0_IRQ_PEND.
0: No effect,
1: Pending. This bit will be pending for user u when Message Queue 0 has
received a new message. Set one to this bit will clear it.
4.13.5.5. MSGBox FIFO Status Register m(Default Value: 0x00000000)
Offset:0x100+N*0x4 (N=0~7)
Register Name: MSGBOXM_FIFO_STATUS_REG
Bit
R/W
Default/Hex
Description
31: 1
/
/
/
0
RO
0x0
FIFO_FULL_FLAG.
0: The Message FIFO queue is not full (space is available),
1: The Message FIFO queue is full.
This FIFO status register has the status related to the message queue.
4.13.5.6. MSGBox Message Status Register m(Default Value: 0x00000000)
Offset:0x140+N*0x4 (N=0~7)
Register Name: MSGBOXM_MSG_STATUS_REG
Bit
R/W
Default/Hex
Description
31:3
/
/
/
2:0
RO
0x0
MSG_NUM.
Number of unread messages in the message queue. Here, limited to four
messages per message queue.
000: There is no message in the message FIFO queue.
001: There is 1 message in the message FIFO queue.
010: There are 2 messages in the message FIFO queue.
011: There are 3 messages in the message FIFO queue.
100: There are 4 messages in the message FIFO queue.
101~111:/
4.13.5.7. MSGBox Message Queue Register (Default Value: 0x00000000)
Offset:0x180+N*0x4 (N=0~7)
Register Name: MSGBOXM_MSG_REG
Bit
R/W
Default/Hex
Description
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