Owners manual

System

4.14.3. Operation Principle

4.14.3.1. Spinlock clock gating and software reset

Spinlock clock gating should be open before using it. Setting Bus Clock Gating Register1 bit[22] to 1 could activate

Spinlock and then de-asserting it's software reset. Setting AHB1 Module Software Reset Register bit[22] to 1 could

de-assert the software reset of Spinlock. If it is no need to use spinlock, both the gating bit and software reset bit should

be set 0.

4.14.3.2. Take and free a spinlock

Checking out SpinLock Register Status is necessary when a processor would like to take a spinlock. This register stores

all 32 lock registers’ status: TAKEN or NOT TAKEN(free).

In order to request to take a spinlock, a processor has to do a read-access to the corresponding lock register. If lock

Writing 0 to a lock register frees the corresponding spinlock. If the lock register is not taken, write-access has no effect.

For a taken spinlock, every processor has the privilege to free this spinlock. But it is suggested that the processor which

has taken the spinlock free it for strictness.

4.14.4. Spinlock Register List

Module Name

Base Address

SPINLOCK

0x01C18000

Offset

Description

SPINLOCK_SYSTATUS_REG

0x0000

Spinlock System Status Register

SPINLOCK_STATUS_REG

0x0010

Spinlock Status Register

SPINLOCK_LOCK_REGN

0x100+N*0x4

Spinlock Register N (N=0~31)

4.14.5. Spinlock Register Description

4.14.5.1. Spinlock System Status Register (Default Value: 0x10000000)

Offset: 0x0

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