Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 228
Task chaining
task chaining id=0
common ctl
symmetric ctl
reserved
key descriptor
iv descriptor
ctr descriptor
data len
src adr0
dst adr7
dst len7
next descriptor(task1)
src len0
reserved[3]
…………
task0 task1
task2
…………
taskn
src adr7
src len7
…
dst adr0
dst len0
…
task chaining id=0
common ctl
symmetric ctl
reserved
key descriptor
iv descriptor
ctr descriptor
data len
src adr0
dst adr7
dst len7
next descriptor(task2)
src len0
reserved[3]
src adr7
src len7
…
dst adr0
dst len0
…
task chaining id=0
common ctl
symmetric ctl
reserved
key descriptor
iv descriptor
ctr descriptor
data len
src adr0
dst adr7
dst len7
next descriptor(taskn)
src len0
reserved[3]
src adr7
src len7
…
dst adr0
dst len0
…
Figure 4-11. Crypto Engine Task Chaining Block Diagram
task_descriptor_queue common control bitmap(32bit)
Bit
Description
31
Each of the tasks to be an interrupt
0:don't interrupt
1:interrupt
29:28
/
27
DMA Read/Write Consistent
0:Send end flag after data write-instruction finished
1:Read data when CE received response of write-instruction ,if write-instruction is non-finished,
waiting until write-instruction finished.
24
/
23:17
MAC Length for CBC-MAC
length=bit[23:17]+1
16
IV_Mode
IV Steady of hash algorithm
0: Constants
1: Arbitrary IV
Notes: It is only used for SHA-1/ SHA-224/SHA-256/SHA-384/SHA-512/MD5 engine.
15
HMAC_SHA1_Last_Block_Flag
When set to "1", it means this is the last block for HMAC-SHA1.
14:9
/
8
CE_OP_DIR
CE Operation Direction
0: Encryption
1: Decryption
7
/
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