Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 230
4: Output feedback (OFB)mode
5: Cipher feedback (CFB)mode
6: CBC-MAC mode
Other: reserved
7:4
/
3:2
CTR_Width
Counter Width for CTR Mode
0: 16-bits Counter
1: 32-bits Counter
2: 64-bits Counter
3: 128-bits Counter
1:0
AES_Key_Size
0: 128-bits
1: 192-bits
2: 256-bits
3: Reserved
4.15.3. Crypto Engine Register List
Module Name
Base Address
CE_N
0x01C15000
CE_S
0x01C15800
Register Name
Offset
Description
CE_TDQ
0x00
Task Descriptor Address
CE_CTR
0x04
Gating Control Register
CE_ICR
0x08
Interrupt Control Register
CE_ISR
0x0c
Interrupt Status Register
CE_TLR
0x10
Task Load Register
CE_ESR
0x18
Task Error type Register
CE_CSSGR
0x1c
Current Source Scatter Group Register
CE_CDSGR
0x20
Current Destination Scatter Group Register
CE_CSAR
0x24
Current Source Address Register
CE_CDAR
0x28
Current Destination Address Register
CE_TPR
0x2c
Throughput Register
4.15.4. Crypto Engine Register Description
4.15.4.1. Crypto Engine Task Descriptor Queue Register(Default Value: 0x00000000)
Offset: 0x00
Register Name: CE_TDQ
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