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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 232
31:1
/
/
/
0
R/W
0
Task_Load
When set , CE starts to load the configure of task from task descriptor queue
and start to perform the task.
4.15.4.6. Crypto Engine Error Status Register(Default Value: 0x00000000)
Offset: 0x18
Register Name: CE_ESR
Bit
R/W
Default/Hex
Description
31:4
/
/
/
3
/
/
/
2
R
0
AES_Access_Keysram_Status
0: AES could perform request if destination address is keysram.
1: AES couldn't perform request if destination address is not keysram.
Notes: Write ‘1’ to clear it.
1
R
0
Task chaining data length error
When the bit is 1,indicate that the configure of data length is error
0
R
0
Task chaining algorithm error
When the bit is 1,indicate that CE is not support the algorithm
4.15.4.7. Crypto Engine Current Source Scatter Group Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: CE_CSSGR
Bit
R/W
Default/Hex
Description
31:16
R
0
The current offset in src adr
These bits indicate that the offset of source address
15:0
R
0
The current source scatter number
When a task is divided to some scatter(max is 8 scatter), these bits indicate
that the scatter is executing for source data
4.15.4.8. Crypto Engine Current Destination Scatter Group Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: CE_CDSGR
Bit
R/W
Default/Hex
Description
31:16
R
0
The current offset in dst adr
These bits indicate that the offset of destination address
15:0
R
0
The current destination scatter number
When a task is divided to some scatter(max is 8 scatter), these bits indicate
that the scatter is executing for destination data
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