Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 241
SMC_MST_ATTRI_REG
0x48
SMC Master Attribute Register
DRM_MASTER_EN_REG
0x50
DRM Master Enable Register
DRM_ILLACCE_REG
0x58
DRM Illegal Access Register
DRM_STATADDR_REG
0x60
DRM Start Address Register
DRM_ENDADDR_REG
0x68
DRM End Address Register
SMC_REGION_SETUP_LO_REG
0x100+N*0x10
Region Setup Low Register N
(N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)
SMC_REGION_SETUP_HI_REG
0x104+N*0x10
Region Setup High Register N
(N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)
SMC_REGION_ATTR_REG
0x108+N*0x10
Region Attribute Register N
(N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)
4.17.4. SMC Register Description
4.17.4.1. SMC Configuration Register(Default Value: 0x00001F0F)
Offset: 0x0
Register Name: SMC_CONFIG_REG
Bit
R/W
Default/Hex
Description
31:14
/
/
/
13:8
R
0x1F
ADDR_WIDTH_RTN.
Address width. Return the width of the AXI address bus.
6’b 000000-6’b011110 reserved.
6’b 011111 = 32-bit
……
6’b 111111 = 64-bit
7:4
/
/
/
3:0
R
0xF
REGIONS_RTN.
Returns the number of the regions that the SMC provides.
4’b0000 = reserved
4’b0001 = 2 regions
……
4’b1111 = 16 regions.
4.17.4.2. SMC Action Register(Default Value: 0x00000001)
Offset: 0x4
Register Name: SMC_ACTION_REG
Bit
R/W
Default/Hex
Description
31:2
/
/
/
1:0
R/W
0x1
SMC_INT_RESP.
Control how the SMC uses the bresps[1:0], rresps[1:0], and smc_int signals
when a region permission failure occurs:
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