Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 243
4.17.4.5. SMC Interrupt Status Register(Default Value: 0x00000000)
Offset: 0x10
Register Name: SMC_INT_STATUS_REG
Bit
R/W
Default/Hex
Description
31:2
/
/
/
1
R
0x0
INT_OVERRUN.
When set to 1, it indicates the occurrence of two or more region permission
failure since the interrupt was last cleared.
0
R
0x0
INT_STATUS.
Return the status of the interrupt.
0: interrupt is inactive.
1: interrupt is active.
4.17.4.6. SMC Interrupt Clear Register(Default Value: 0x00000000)
Offset: 0x14
Register Name: SMC_INT_CLEAR_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
SMC_CLR_REG.
Write any value to the int_clear register sets the :
Status bit to 0 in the int_status register
Overrun bit to 0 in the int_status register.
Note: It will be auto cleared after the write operation.
4.17.4.7. SMC Master Bypass Register(Default Value: 0xFFFFFFFF)
Offset: 0x18
Register Name: SMC_MST_BYP_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
0xFFFFFFFF
SMC_MASTER_BYPASS_EN.
SMC Master n Bypass Enable.
(n = 0~31, see the Table 4-2. MASTER and MASTER ID for detail.)
Note: Bit[31:0] stand for Master ID [31:0]
If the master n bypass enable is set to 0, the master n access must be
through the SMC.
0: Bypass Disable
1: Bypass Enable.
4.17.4.8. SMC Master Secure Register(Default Value: 0x00000000)
Offset: 0x1C
Register Name: SMC_MST_SEC_REG
Bit
R/W
Default/Hex
Description
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