Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 244
31:0
R/W
0x0
SMC_MASTER_SEC.
SMC Master n Secure Configuration.(n = 0~31，see the Table 4-2 for detail)
0: secure
1: non-secure.
4.17.4.9. SMC Fail Address Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: SMC_FAIL_ADDR_REG
Bit
R/W
Default/Hex
Description
31:0
R
0x0
FIRST_ACCESS_FAIL.
Return the address bits [31:0] of the first access to fail a region permission
check after the interrupt was cleared.
For external 16-bit DDR2, the address [2:0] is fixed to zero.
For external 32-bit DDR2 and 16-bit DDR3, the address [3:0] is fixed to zero.
For external 32-bit DDR3, the address [4:0] is fixed to zero.
Note:If the master ID=”SRAM” and the register value is between 0x80000 to 0xBFFFF,
the real address should be divide by 4.
4.17.4.10. SMC Fail Control Register(Default Value: 0x00000000)
Offset: 0x28
Register Name: SMC_FAIL_CTRL_REG
Bit
R/W
Default/Hex
Description
31:25
/
/
/
24
R
0x0
READ_WRITE.
This bit indicates whether the first access to fail a region permission check
was a write or read as:
0 = read access
1 = write access.
23:22
/
/
/
21
R
0x0
NON_SECURE.
After clearing the interrupt status, this bit indicates whether the first access
to fail a region permission check was non-secure. Read as:
0 = secure access
1 = non-secure access
20
R
0x0
PRIVILEGED.
After clearing the interrupt status, this bit indicates whether the first access
to fail a region permission check was privileged. Read as:
0 = unprivileged access.
1 = privileged access
19:0
/
/
/
confidential