Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 246
4.17.4.14. SMC Master Attribute Register(Default Value: 0x00000000)
Offset: 0x48
Register Name: SMC_MST_ATTRI_REG
Bit
R/W
Default/Hex
Description
31:0
R/W
0x0
MST_ATTRI.
0: The secure attribute of master is up to master security extensions;
1: The secure attribute of master is up to Master Secure Register.
4.17.4.15. DRM Master Enable Register(Default Value: 0x00000000)
Offset: 0x50
Register Name: DRM_MASTER_EN_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
DRM_EN.
DRM enable.
30:12
/
/
/
13
R/W
0x0
GPU_WRITE_EN
GPU write enable.
12
R/W
0x0
GPU_READ_EN
GPU read enable.
11:8
/
/
/
7
R/W
0x0
DE_INTERLACE
DE_ INTERLACE enable.
6
R/W
0x0
DE_RT-WB
DE_RT-WB enable.
5
R/W
0x0
DE_RT-MIXER1
DE_RT-MIXER1 enable.
4
R/W
0x0
DE_RT-MIXER0
DE_RT-MIXER0 enable.
3:1
/
/
/
0
R/W
0x0
VE_ENCODE_EN
VE encode enable.
4.17.4.16. DRM Illegal Access Register(Default Value: 0x00000000)
Offset: 0x58
Register Name: DRM_ILLACCE_REG0
Bit
R/W
Default/Hex
Description
31:0
RO
0x0
DRM_ILLACCE_REG.
When a master, which is non-secure, accesses the DRM space, then the
relevant bit will be set up. See Table 4-2 for detail.
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