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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 262
10: Continue Mode
11:8
R/W
0x1
LEVELA_B_CNT.
Level A to Level B time threshold select, judge ADC convert value in level A
to level B in n+1 samples
7
R/W
0X0
KEY_ADC_HOLD_KEY_EN
KEY_ADC Hold Key Enable
0: Disable
1: Enable
6
R/W
0x1
KEY_ADC_HOLD_EN.
KEY_ADC Sample hold Enable
0: Disable
1: Enable
5: 4
R/W
0x2
LEVELB_VOL.
Level B Corresponding Data Value setting (the real voltage value)
00: 0x3C (~1.9v)
01: 0x39 (~1.8v)
10: 0x36 (~1.7v)
11: 0x33 (~1.6v)
3: 2
R/W
0x2
KEY_ADC_SAMPLE_RATE.
KEY_ADC Sample Rate
00: 250 Hz
01: 125 Hz
10: 62.5 Hz
11: 32.25 Hz
1
/
/
/
0
R/W
0x0
KEY_ADC_EN.
KEY_ADC enable
0: Disable
1: Enable
4.20.4.2. KEY_ADC Interrupt Control Register (Default Value: 0x00000000)
Offset: 0x04
Register Name: KEY_ADC_INTC_REG
Bit
R/W
Default/Hex
Description
31:5
/
/
/
4
R/W
0x0
ADC_KEYUP_IRQ_EN.
ADC Key Up IRQ Enable
0: Disable
1: Enable
3
R/W
0x0
ADC_ALRDY_HOLD_IRQ_EN.
ADC Already Hold IRQ Enable
0: Disable
1: Enable
2
R/W
0x0
ADC_HOLD_IRQ_EN.
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