Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 272
When TX FIFO Available Room Less Than Or Equal N, DRQ Request Will Be
De-Asserted. N Is Defined Here:
00: IRQ/DRQ De-Asserted When WLEVEL > TXTL
01: 4
10: 8
11: 16
20:15
/
/
/
14:8
R/W
0XF
TX_TRIG_LEVEL
TX FIFO Empty Trigger Level (TXTL[12:0])
Interrupt and DMA request trigger level for TX FIFO normal condition.
IRQ/DRQ Generated when WLEVEL ≤ TXTL
Notes:
1. WLEVEL represents the number of valid samples in the TX FIFO
2. Only TXTL[6:0] valid when TXMODE = 0
7
R/W
0X0
ADDA_LOOP_EN
ADDA Loop Enable
0: Disable
1: Enable
6
R/W
0X0
DAC_MONO_EN
DAC Mono Enable
0: Stereo, 64 Levels FIFO
1: Mono, 128 Levels FIFO
When Enabled, L & R Channel Send Same Data
5
R/W
0X0
TX_SAMPLE_BITS
Transmitting Audio Sample Resolution
0: 16 bits
1: 24 bits
4
R/W
0X0
DAC_DRQ_EN
DAC FIFO Empty DRQ Enable
0: Disable
1: Enable
3
R/W
0X0
DAC_IRQ_EN
DAC FIFO Empty IRQ Enable
0: Disable
1: Enable
2
R/W
0X0
FIFO_UNDERRUN_IRQ_EN
DAC FIFO Under Run IRQ Enable
0: Disable
1: Enable
1
R/W
0X0
FIFO_OVERRUN_IRQ_EN
DAC FIFO Over Run IRQ Enable
0: Disable
1: Enable
0
R/W
0X0
FIFO_FLUSH
DAC FIFO Flush
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