Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 273
Write ‘1’ To Flush TX FIFO, Self Clear to ‘0’
4.21.5.3. 0x08 DAC FIFO Status Register(Default Value: 0x00800088)
Offset: 0x08
Register Name: AC_DAC_FIFOS
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23
R
0x1
TX_EMPTY
TX FIFO Empty
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO (>= 1 word)
22:8
R
0x80
TXE_CNT
TX FIFO Empty Space Word Counter
7:4
/
/
/
3
R/W
0x1
TXE_INT
TX FIFO Empty Pending Interrupt
0: No Pending IRQ
1: FIFO Empty Pending Interrupt
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition fails
2
R/W
0x0
TXU_INT
TX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1: FIFO Under run Pending Interrupt
Write ‘1’ to clear this interrupt
1
R/W
0x0
TXO_INT
TX FIFO Overrun Pending Interrupt
0: No Pending Interrupt
1: FIFO Overrun Pending Interrupt
Write ‘1’ to clear this interrupt
0
/
/
/
4.21.5.4. 0x10 ADC FIFO Control Register(Default Value: 0x00000F00)
Offset: 0x10
Register Name: AC_ADC_FIFOC
Bit
R/W
Default/Hex
Description
31:29
R/W
0X0
ADFS
Sample Rate of ADC
000: 48KHz
010: 24KHz
100: 12KHz
110: Reserved
001: 32KHz
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