Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 274
011: 16KHz
101: 8KHz
111: Reserved
44.1KHz/22.05KHz/11.025KHz can be supported by Audio PLL Configure Bit
28
R/W
0X0
EN_AD
ADC Digital Part Enable
0: Disable
1: Enable
27:25
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24
R/W
0X0
RX_FIFO_MODE
RX FIFO Output Mode (Mode 0, 1)
0: Expanding ‘0’ at LSB of TX FIFO register
1: Expanding received sample sign bit at MSB of TX FIFO register
For 24-bits received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[23:0], 8’h0}
Mode 1: Reserved
For 16-bits received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[23:8], 16’h0}
Mode 1: RXDATA[31:0] = {16{FIFO_O[23]}, FIFO_O[23:8]}
23:19
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18:17
R/W
0X0
ADCFDT
ADC FIFO Delay Time For writing Data after EN_AD
00:5ms
01:10ms
10:20ms
11:30ms
16
R/W
0X0
ADCDFEN
ADC FIFO Delay Function For writing Data after EN_AD
0: Disable
1: Enable
15:13
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12:8
R/W
0XF
RX_FIFO_TRG_LEVEL
RX FIFO Trigger Level (RXTL[4:0])
Interrupt and DMA request trigger level for RX FIFO normal condition
IRQ/DRQ Generated when WLEVEL < RXTL[4:0]
Notes:
WLEVEL represents the number of valid samples in the RX FIFO
7
R/W
0X0
ADC_MONO_EN
ADC Mono Enable
0: Stereo, 16 levels FIFO
1: mono, 32 levels FIFO
When set to ‘1’, Only left channel samples are recorded
6
R/W
0x0
RX_SAMPLE_BITS
Receiving Audio Sample Resolution
0: 16 bits
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