Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 275
1: 24 bits
5
/
/
/
4
R/W
0X0
ADC_DRQ_EN
ADC FIFO Data Available DRQ Enable
0: Disable
1: Enable
3
R/W
0X0
ADC_IRQ_EN
ADC FIFO Data Available IRQ Enable
0: Disable
1: Enable
2
/
/
1
R/W
0X0
ADC_OVERRUN_IRQ_EN
ADC FIFO Over Run IRQ Enable
0: Disable
1: Enable
0
R/W
0X0
ADC_FIFO_FLUSH
ADC FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’
4.21.5.5. 0x14 ADC FIFO Status Register(Default Value: 0x00000000)
Offset: 0x14
Register Name: AC_ADC_FIFOS
Bit
R/W
Default/Hex
Description
31:24
/
/
/
23
R
0X0
RXA
RX FIFO Available
0: No available data in RX FIFO
1: More than one sample in RX FIFO (>= 1 word)
22:14
/
/
/
13:8
R
0X0
RXA_CNT
RX FIFO Available Sample Word Counter
7:4
/
/
/
3
R/W
0X0
RXA_INT
RX FIFO Data Available Pending Interrupt
0: No Pending IRQ
1: Data Available Pending IRQ
Write ‘1’ to clear this interrupt or automatic clear if interrupt condition fails
2
/
/
/
1
R/W
0X0
RXO_INT
RX FIFO Overrun Pending Interrupt
0: No Pending IRQ
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt
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