Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 276
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4.21.5.6. 0x18 ADC RX DATA Register(Default Value: 0x00000000)
Offset: 0x18
Register Name: AC_ADC_RXDATA
Bit
R/W
Default/Hex
Description
31:0
R
0X0
RX_DATA
RX Sample
Host can get one sample by reading this register. The left channel sample data
is first and then the right channel sample.
4.21.5.7. 0x20 DAC TX DATA Register(Default Value: 0x00000000)
Offset: 0x20
Register Name: AC_DAC_TXDATA
Bit
R/W
Default/Hex
Description
31:0
W
0X0
TX_DATA
Transmitting left, right channel sample data should be written this register
one by one. The left channel sample data is first and then the right channel
sample
4.21.5.8. 0x40 DAC TX Counter Register(Default Value: 0x00000000)
Offset: 0x40
Register Name: AC_DAC_CNT
Bit
R/W
Default/Hex
Description
31:0
R/W
0X0
TX_CNT
TX Sample Counter
The audio sample number of sending into TXFIFO. When one sample is put
into TXFIFO by DMA or by host IO, the TX sample counter register increases by
one. The TX sample counter register can be set to any initial valve at any time.
After been updated by the initial value, the counter register should count on
base of this initial value
Notes: It is used for Audio/ Video Synchronization
4.21.5.9. 0x44 ADC RX Counter Register(Default Value: 0x00000000)
Offset: 0x44
Register Name: AC_ADC_CNT
Bit
R/W
Default/Hex
Description
31:0
R/W
0X0
RX_CNT
RX Sample Counter
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