Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 285
01 : 0.9375db
10 : 1.9375db
11 : 3db
7:6
/
/
/
5
R/W
0
The input signal average filter coefficient setting
0 : is the reg94/reg98
1 : is the reg80/reg88;
4
R/W
0
AGC output when the channel in noise state
0 : output is zero
1 : output is the input data
3
/
/
/
2
R/W
0
Right energy default value setting(include the input and output)
0 : min
1 : max
1 :0
R/W
00
Right channel gain hysteresis setting.
The different between target level and the signal level must larger than the
hysteresis when the gain change.
00 : 0.4375db
01 : 0.9375db
10 : 1.9375db
11 : 3db
4.21.5.25. 0x100 DAC DRC High HPF Coef Register(Default Value: 0x000000FF)
Offset: 0x100
Register Name: AC_DAC_DRC_HHPFC
Bit
R/W
Default/Hex
Description
15:11
/
/
/
10:0
R/W
0xff
HPF coefficient setting and the data is 3.24 format.
4.21.5.26. 0x104 DAC DRC Low HPF Coef Register(Default Value: 0x0000FAC1)
Offset: 0x104
Register Name: AC_DAC_DRC_LHPFC
Bit
R/W
Default/Hex
Description
15:0
R/W
0xFAC1
HPF coefficient setting and the data is 3.24 format.
4.21.5.27. 0x108 DAC DRC Control Register(Default Value: 0x00000080)
Offset: 0x108
Register Name: AC_DAC_DRC_CTRL
Bit
R/W
Default/Hex
Description
15
R
0
DRC delay buffer data output state when drc delay function is enble and the
drc funciton disable. After disable drc function and this bit go to 0, the user
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