Manualshelf

Owners manual

ManualsBrandsLinkSprite ManualsComputer HardwarepcDuino4 Nano A33 Quad Core Single Board Computer
281282283284285286287288289290
System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 288
4.21.5.32. 0x11C DAC DRC Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF)
Offset: 0x11C
Register Name: AC_DAC_DRC_LPFHRT
Bit
R/W
Default/Hex
Description
15:11
/
/
/
10:0
R/W
0x00FF
The left peak filter release time parameter setting, which determine by the
equation that RT = exp(-2.2Ts/tr). The format is 3.24. (100ms)
4.21.5.33. 0x120 DAC DRC Left Peak Filter Low Release Time Coef Register(Default Value: 0x0000E1F8)
Offset: 0x120
Register Name: AC_DAC_DRC_LPFLRT
Bit
R/W
Default/Hex
Description
15:0
R/W
0xE1F8
The left peak filter release time parameter setting, which determine by the
equation that RT = exp(-2.2Ts/tr). The format is 3.24. (100ms)
4.21.5.34. 0x124 DAC DRC Right Peak filter High Release Time Coef Register(Default Value: 0x0000_00FF)
Offset: 0x124
Register Name: AC_DAC_DRC_RPFHRT
Bit
R/W
Default/Hex
Description
15:11
/
/
/
10:0
R/W
0x00FF
The left peak filter attack time parameter setting, which determine by the
equation that RT = exp(-2.2Ts/tr). The format is 3.24. (100ms)
4.21.5.35. 0x128 DAC DRC Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8)
Offset: 0x128
Register Name: AC_DAC_DRC_RPFLRT
Bit
R/W
Default/Hex
Description
15:0
R/W
0xE1F8
The left peak filter release time parameter setting, which determine by the
equation that AT = exp(-2.2Ts/tr). The format is 3.24. (100ms)
4.21.5.36. 0x12C DAC DRC Left RMS Filter High Coef Register(Default Value: 0x00000001)
Offset: 0x12C
Register Name: AC_DAC_DRC_LRMSHAT
Bit
R/W
Default/Hex
Description
15:11
/
/
/
10:0
R/W
0x0001
The left RMS filter average time parameter setting, which determine by the
equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24. (10ms)
confidential