Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 289
4.21.5.37. 0x130 DAC DRC Left RMS Filter Low Coef Register(Default Value: 0x00002BAF)
Offset: 0x130
Register Name: AC_DAC_DRC_LRMSLAT
Bit
R/W
Default/Hex
Description
15:0
R/W
0x2BAF
The left RMS filter average time parameter setting, which determine by the
equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24. (10ms)
4.21.5.38. 0x134 DAC DRC Right RMS Filter High Coef Register(Default Value: 0x00000001)
Offset: 0x134
Register Name: AC_DAC_DRC_RRMSHAT
Bit
R/W
Default/Hex
Description
15:11
/
/
/
10:0
R/W
0x0001
The right RMS filter average time parameter setting, which determine by the
equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24. (10ms)
4.21.5.39. 0x138 DAC DRC Right RMS Filter Low Coef Register(Default Value: 0x00002BAF)
Offset: 0x138
Register Name: AC_DAC_DRC_RRMSLAT
Bit
R/W
Default/Hex
Description
15:0
R/W
0x2BAF
The right RMS filter average time parameter setting, which determine by the
equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24. (10ms)
4.21.5.40. 0x13C DAC DRC Compressor Threshold High Setting Register(Default Value: 0x000006A4)
Offset: 0x13C
Register Name: AC_DAC_DRC_HCT
Bit
R/W
Default/Hex
Description
15:0
R/W
0x06A4
The compressor threshold setting, which set by the equation that CTin =
-CT/6.0206. The format is 8.24 (-40dB)
4.21.5.41. 0x140 DAC DRC Compressor Threshold High Setting Register(Default Value: 0x0000_D3C0)
Offset: 0x140
Register Name: AC_DAC_DRC_LCT
Bit
R/W
Default/Hex
Description
15:0
R/W
0xD3C0
The compressor threshold setting, which set by the equation that CTin =
-CT/6.0206. The format is 8.24 (-40dB)
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