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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 291
4.21.5.47. 0x158 DAC DRC Limiter Theshold Low Setting Register(Default Value: 0x0000_34F0)
Offset: 0x158
Register Name: AC_DAC_DRC_LLT
Bit
R/W
Default/Hex
Description
15:0
R/W
0x34F0
The limiter threshold setting, which set by the equation that LTin = -LT/6.0206,
The format is 8.24. (-10dB)
4.21.5.48. 0x15C DAC DRC Limiter Slope High Setting Register(Default Value: 0x0000_0005)
Offset: 0x15C
Register Name: AC_DAC_DRC_HKl
Bit
R/W
Default/Hex
Description
15:11
/
/
/
13:0
R/W
0x0005
The slope of the limiter which determine by the equation that Kl = 1/R, there,
R is the ratio of the limiter, which always is interger. The format is 8.24. (50 :1)
4.21.5.49. 0x160 DAC DRC Limiter Slope Low Setting Register(Default Value: 0x00001EB8)
Offset: 0x160
Register Name: AC_DAC_DRC_LKl
Bit
R/W
Default/Hex
Description
15:0
R/W
0x1EB8
The slope of the limiter which determine by the equation that Kl = 1/R, there,
R is the ratio of the limiter, which always is interger. The format is 8.24. (50 :1)
4.21.5.50. 0x164 DAC DRC Limiter High Output at Limiter Threshold(Default Value: 0x0000FBD8)
Offset: 0x164
Register Name: AC_DAC_DRC_HOPL
Bit
R/W
Default/Hex
Description
15:0
R/W
0xFBD8
The output of the limiter which determine by equation OPT/6.0206. The
format is 8.24 (-25dB)
4.21.5.51. 0x168 DAC DRC Limiter Low Output at Limiter Threshold(Default Value: 0x0000FBA7)
Offset: 0x168
Register Name: AC_DAC_DRC_LOPL
Bit
R/W
Default/Hex
Description
15:0
R/W
0xFBA7
The output of the limiter which determine by equation OPT/6.0206. The
format is 8.24 (-25dB)
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