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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 296
4.21.5.72. 0x200 ADC DRC High HPF Coef Register(Default Value: 0x000000FF)
Offset: 0x200
Register Name: AC_ADC_DRC_HHPFC
Bit
R/W
Default/Hex
Description
15:11
/
/
/
10:0
R/W
0xFF
HPF coefficient setting and the data is 3.24 format.
4.21.5.73. 0x204 ADC DRC Low HPF Coef Register(Default Value: 0x0000FAC1)
Offset: 0x204
Register Name: AC_ADC_DRC_LHPFC
Bit
R/W
Default/Hex
Description
15:0
R/W
0xFAC1
HPF coefficient setting and the data is 3.24 format.
4.21.5.74. 0x208 ADC DRC Control Register(Default Value: 0x00000080)
Offset: 0x208
Register Name: AC_ADC_DRC_CTRL
Bit
R/W
Default/Hex
Description
15
R
0
DRC delay buffer data output state when drc delay function is enable and the
drc function disable. After disable drc function and this bit go to 0, the user
should write the drc delay function bit to 0;
0 : not complete
1 : is complete
14:10
/
/
/
13:8
R/W
0
Signal delay time setting
6'h00 : (8x1)fs
6'h01 : (8x2)fs
6'h02 : (8x3)fs
----------------------------------------
6'h2e : (8*47)fs
6'h2f : (8*48)fs
6'h30 -- 6'h3f : (8*48)fs
Delay time = 8*(n+1)fs, n<6'h30;
When the delay function is disable, the signal delay time is unused.
7
R/W
0x1
The delay buffer use or not when the drc disable and the drc buffer data output
completely
0 : don't use the buffer
1 : use the buffer
6
R/W
0x0
DRC gain max limit enable
0 : disable
1 : enable
5
R/W
0x0
DRC gain min limit enable. when this function enable, it will overwrite the noise
detect function.
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