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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 301
4.21.5.92. 0x250 ADC DRC Compressor Low Output at Compressor Threshold Register(Default Value:
0x00002C3F)
Offset: 0x250
Register Name: AC_ADC_DRC_LOPC
Bit
R/W
Default/Hex
Description
15:0
R/W
0x2C3F
The output of the compressor which determine by the equation OPC/6.0206
The format is 8.24 (-40dB)
4.21.5.93. 0x254 ADC DRC Limiter Theshold High Setting Register(Default Value: 0x000001A9)
Offset: 0x254
Register Name: AC_ADC_DRC_HLT
Bit
R/W
Default/Hex
Description
15:0
R/W
0x01A9
The limiter threshold setting, which set by the equation that LTin = -LT/6.0206,
The format is 8.24. (-10dB)
4.21.5.94. 0x258 ADC DRC Limiter Theshold Low Setting Register(Default Value: 0x000034F0)
Offset: 0x258
Register Name: AC_ADC_DRC_LLT
Bit
R/W
Default/Hex
Description
15:0
R/W
0x34F0
The limiter threshold setting, which set by the equation that LTin = -LT/6.0206,
The format is 8.24. (-10dB)
4.21.5.95. 0x25C ADC DRC Limiter Slope High Setting Register(Default Value: 0x00000005)
Offset: 0x25C
Register Name: AC_ADC_DRC_HKl
Bit
R/W
Default/Hex
Description
15:11
/
/
/
13:0
R/W
0x0005
The slope of the limiter which determine by the equation that Kl = 1/R, there, R
is the ratio of the limiter, which always is interger. The format is 8.24. (50 :1)
4.21.5.96. 0x260 ADC DRC Limiter Slope Low Setting Register(Default Value: 0x1EB8)
Offset: 0x260
Register Name: AC_ADC_DRC_LKl
Bit
R/W
Default/Hex
Description
15:0
R/W
0x1EB8
The slope of the limiter which determine by the equation that Kl = 1/R, there, R
is the ratio of the limiter, which always is interger. The format is 8.24. (50 :1)
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