Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 307
WDAT[7:0]：Write Data；
RDAT[7:0]： Read Data.
APB0
W/R
Addr[4:0]
Data_in[7:0]
Data_out[7:0]
Bit
RST
28
32-29
/
27-23
/
24
WR
15-8
Data_in
7-0
Data_out
20-16
Addr
Reset
23-21
/
25 8-bit
registers
CPUS
0x01F015C0
Figure 4-16. Audio Codec Analog Register Diagram
4.21.6.2. 0x00 LINEOUT PA Gating Control Register(Default Value: 0x00)
Offset:0x00
Register Name: LINEOUT_PA_GAT
Bit
R/W
Default/Hex
Description
7
R/W
0x0
PA clock gating control;
when system VDD is off and Audio analog channel is working, this bit must be
set to 1, because the PA clock come from system VDD domain. When this bit is
1, the Zero cross over function will be disabled automatically.
0: not gating; 1: gating
6:0
/
/
/
4.21.6.3. 0x01 Left Output Mixer Source Select Control Register(Default Value: 0x00)
Offset:0x01
Register Name: LOMIXSC
Bit
R/W
Default/Hex
Description
7
/
/
/
6:0
R/W
0x0
LMIXMUTE
Left Output Mixer Mute Control
0-Mute, 1-Not Mute
Bit 6: MIC1 Boost Stage
Bit 5: MIC2 Boost Stage
Bit 4: /
Bit 3: /
Bit 2: LINEINL
Bit 1: Left Channel DAC
Bit 0: Right Channel DAC
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