Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 316
4.22. Port Controller(CPU-PORT)
The chip has 7 ports for multi-functional input/out pins. They are shown below:
 Port A(PA): 22 input/output port
 Port C(PC): 19 input/output port
 Port D(PD): 18 input/output port
 Port E(PE) : 16 input/output port
 Port F(PF) : 7 input/output port
 Port G(PG) : 14 input/output port
 Port L(PL) : 12 input/output port
For various system configurations, these ports can be easily configured by software. All these ports can be configured as
GPIO if multiplexed functions are not used. The total 2 group external PIO interrupt sources are supported and interrupt
mode can be configured by software.
4.22.1. Port Controller Register List
Module Name
Base Address
PIO
0x01C20800
Register Name
Offset
Description
Pn_CFG0
n*0x24+0x00
Port n Configure Register 0 (n from 0 to 6)
Pn_CFG1
n*0x24+0x04
Port n Configure Register 1 (n from 0 to 6)
Pn_CFG2
n*0x24+0x08
Port n Configure Register 2 (n from 0 to 6)
Pn_CFG3
n*0x24+0x0C
Port n Configure Register 3 (n from 0 to 6)
Pn_DAT
n*0x24+0x10
Port n Data Register (n from 0 to 6)
Pn_DRV0
n*0x24+0x14
Port n Multi-Driving Register 0 (n from 0 to 6)
Pn_DRV1
n*0x24+0x18
Port n Multi-Driving Register 1 (n from 0 to 6)
Pn_PUL0
n*0x24+0x1C
Port n Pull Register 0 (n from 0 to 6)
Pn_PUL1
n*0x24+0x20
Port n Pull Register 1 (n from 0 to 6)
PA_INT_CFG0
0x200+0*0x20+0x00
PIO Interrrupt Configure Register 0
PA _INT_CFG1
0x200+0*0x20+0x04
PIO Interrrupt Configure Register 1
PA _INT_CFG2
0x200+0*0x20+0x08
PIO Interrrupt Configure Register 2
PA _INT_CFG3
0x200+0*0x20+0x0C
PIO Interrrupt Configure Register 3
PA _INT_CTL
0x200+0*0x20+0x10
PIO Interrupt Control Register
PA _INT_STA
0x200+0*0x20+0x14
PIO Interrupt Status Register
PA_INT_DEB
0x200+0*0x20+0x18
PIO Interrupt Debounce Register
PG_INT_CFG0
0x200+1*0x20+0x00
PIO Interrrupt Configure Register 0
PG _INT_CFG1
0x200+1*0x20+0x04
PIO Interrrupt Configure Register 1
PG _INT_CFG2
0x200+1*0x20+0x08
PIO Interrrupt Configure Register 2
PG _INT_CFG3
0x200+1*0x20+0x0C
PIO Interrrupt Configure Register 3
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