Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 328
000:Input 001:Output
010:RGMII_TXCK/MII_TXCK/RMII_TXCK 011:Reserved
100:Reserved 101:Reserved
110:Reserved 111:IO Disable
15
/
/
/
14:12
R/W
0x7
PD11_SELECT
000:Input 001:Output
010:RGMII_NULL/MII_CRS/RMII_NULL 011:Reserved
100:Reserved 101:Reserved
110:Reserved 111:IO Disable
11
/
/
/
10:8
R/W
0x7
PD10_SELECT
000:Input 001:Output
010:RGMII_TXD0/MII_TXD0/RMII_TXD0 011:Reserved
100:Reserved 101:Reserved
110:Reserved 111:IO Disable
7
/
/
/
6:4
R/W
0x7
PD9_SELECT
000:Input 001:Output
010:RGMII_TXD1/MII_TXD1/RMII_TXD1 011:Reserved
100:Reserved 101:Reserved
110:Reserved 111:IO Disable
3
/
/
/
2:0
R/W
0x7
PD8_SELECT
000:Input 001:Output
010:RGMII_TXD2/MII_TXD2/RMII_NULL 011:Reserved
100:Reserved 101:Reserved
110:Reserved 111:IO Disable
4.22.2.21. PD Configure Register 2 (Default Value: 0x00000077)
Offset: 0x74
Register Name: PD_CFG2_REG
Bit
R/W
Default/Hex
Description
31:7
/
/
/
6:4
R/W
0x7
PD17_SELECT
000:Input 001:Output
010:MDIO 011:Reserved
100:Reserved 101:Reserved
110:Reserved 111:IO Disable
3
/
/
/
2:0
R/W
0x7
PD16_SELECT
000:Input 001:Output
010:MDC 011:Reserved
100:Reserved 101:Reserved
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