Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 329
110:Reserved 111:IO Disable
4.22.2.22. PD Configure Register 3 (Default Value: 0x00000000)
Offset: 0x78
Register Name: PD_CFG3_REG
Bit
R/W
Default/Hex
Description
31:0
/
/
/
4.22.2.23. PD Data Register (Default Value: 0x00000000)
Offset: 0x7C
Register Name: PD_DATA _REG
Bit
R/W
Default/Hex
Description
31:18
/
/
/
17:0
R/W
0x0
PD_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.
4.22.2.24. PD Multi-Driving Register 0 (Default Value: 0x55555555)
Offset: 0x80
Register Name: PD_DRV0_REG
Bit
R/W
Default/Hex
Description
[2i+1:2i]
(i=0~15)
R/W
0x1
PD_DRV
PD[n] Multi-Driving SELECT (n = 0~15)
00: Level 0 01: Level 1
10: Level 2 11: Level 3
4.22.2.25. PD Multi-Driving Register 1 (Default Value: 0x00000005)
Offset: 0x84
Register Name: PD_DRV1_REG
Bit
R/W
Default/Hex
Description
31:4
/
/
/
[2i+1:2i]
(i=0~1)
R/W
0x1
PD_DRV
PD[n] Multi-Driving Select (n = 16~17)
00: Level 0 01: Level 1
10: Level 2 11: Level 3
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