Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 339
2:0
R/W
0x7
PG8_SELECT
000:Input 001:Output
010:UART1_RTS 011: Reserved
100:Reserved 101:Reserved
110:PG_EINT8 111:IO Disable
4.22.2.48. PG Configure Register 2 (Default Value: 0x00000000)
Offset: 0xE0
Register Name: PG_CFG2_REG
Bit
R/W
Default/Hex
Description
31:0
/
/
/
4.22.2.49. PG Configure Register 3 (Default Value: 0x00000000)
Offset: 0xE4
Register Name: PG_CFG3_REG
Bit
R/W
Default/Hex
Description
31:0
/
/
/
4.22.2.50. PG Data Register (Default Value: 0x00000000)
Offset: 0xE8
Register Name: PG_DATA_REG
Bit
R/W
Default/Hex
Description
31:14
/
/
/
13:0
R/W
0x0
PG_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.
4.22.2.51. PG Multi-Driving Register 0 (Default Value: 0x05555555)
Offset: 0xEC
Register Name: PG_DRV0_REG
Bit
R/W
Default/Hex
Description
31:28
/
/
/
[2i+1:2i]
(i=0~13)
R/W
0x1
PF_DRV
PF[n] Multi-Driving SELECT (n = 0~13)
00: Level 0 01: Level 1
10: Level 2 11: Level 3
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