Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 345
4.23. Port Controller(CPUs-PORT)
The chip has 1 port for multi-functional input/out pins. They are shown below:
 Port L(PL):12 input/output port
For various system configurations, these ports can be easily configured by software. All these ports can be configured as
GPIO if multiplexed functions not used. The external PIO interrupt sources are supported and interrupt mode can be
configured by software.
4.23.1. Port Controller Register List
Module Name
Base Address
PIO
0x01F02C00
Register Name
Offset
Description
PL_CFG0
0*0x24+0x00
Port L Configure Register 0
PL_CFG1
0*0x24+0x04
Port L Configure Register 1
PL_CFG2
0*0x24+0x08
Port L Configure Register 2
PL_CFG3
0*0x24+0x0C
Port L Configure Register 3
PL_DAT
0*0x24+0x10
Port L Data Register
PL_DRV0
0*0x24+0x14
Port L Multi-Driving Register 0
PL_DRV1
0*0x24+0x18
Port L Multi-Driving Register 1
PL_PUL0
0*0x24+0x1C
Port L Pull Register 0
PL_PUL1
0*0x24+0x20
Port L Pull Register 1
PL_INT_CFG0
0x200+0*0x20+0x00
PIO Interrrupt Configure Register 0
PL _INT_CFG1
0x200+0*0x20+0x04
PIO Interrrupt Configure Register 1
PL _INT_CFG2
0x200+0*0x20+0x08
PIO Interrrupt Configure Register 2
PL _INT_CFG3
0x200+0*0x20+0x0C
PIO Interrrupt Configure Register 3
PL _INT_CTL
0x200+0*0x20+0x10
PIO Interrupt Control Register
PL _INT_STA
0x200+0*0x20+0x14
PIO Interrupt Status Register
PL _INT_DEB
0x200+0*0x20+0x18
PIO Interrupt Debounce Register
4.23.2. Port Controller Register Description
4.23.2.1. PL Configure Register 0 (Default Value: 0x77777777)
Offset: 0x00
Register Name: PL_CFG0_REG
Bit
R/W
Default/Hex
Description
31
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