Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 348
31:0
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4.23.2.5. PL Data Register (Default Value: 0x00000000)
Offset: 0x10
Register Name: PL_DATA_REG
Bit
R/W
Default/Hex
Description
31:12
/
/
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11:0
R/W
0
PL_DAT
If the port is configured as input, the corresponding bit is the pin state. If
the port is configured as output, the pin state is the same as the
corresponding bit. The read bit value is the value setup by software. If the
port is configured as functional pin, the undefined value will be read.
4.23.2.6. PL Multi-Driving Register 0 (Default Value: 0x00555555)
Offset: 0x14
Register Name: PL_DRV0
Bit
R/W
Default/Hex
Description
31:24
/
/
/
[2i+1:2i]
(i=0~11)
R/W
0x1
PL_DRV
PL[n] Multi-Driving Select (n = 0~11)
00: Level 0 01: Level 1
10: Level 2 11: Level 3
4.23.2.7. PL Multi-Driving Register 1 (Default Value: 0x00000000)
Offset: 0x18
Register Name: PL_DRV1
Bit
R/W
Default/Hex
Description
31:0
/
/
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4.23.2.8. PL PULL Register 0 (Default Value: 0x00000005)
Offset: 0x1C
Register Name: PL_PULL0
Bit
R/W
Default/Hex
Description
31:24
/
/
/
[2i+1:2i]
(i=0~11)
R/W
0x5
PL_PULL
PL[n] Pull-up/down Select (n = 0~11)
00: Pull-up/down disable 01: Pull-up
10: Pull-down 11: Reserved
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