Owners manual

H3
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 35
5.3.7.6. SD Block Count Register (Default Value: 0x00000200) ............................................................. 386
5.3.7.7. SD Command Register (Default Value: 0x00000000) ................................................................ 386
5.3.7.8. SD Command Argument Register (Default Value: 0x00000000) ............................................... 388
5.3.7.9. SD Response 0 Register (Default Value: 0x00000000) .............................................................. 388
5.3.7.10. SD Response 1 Register (Default Value: 0x00000000) ............................................................ 388
5.3.7.11. SD Response 2 Register (Default Value: 0x00000000) ............................................................ 388
5.3.7.12. SD Response 3 Register (Default Value: 0x00000000) ............................................................ 389
5.3.7.13. SD Interrupt Mask Register (Default Value: 0x00000000) ...................................................... 389
5.3.7.14. SD Masked Interrupt Status Register (Default Value: 0x00000000) ....................................... 389
5.3.7.15. SD Raw Interrupt Status Register (Default Value: 0x00000000) ............................................. 390
5.3.7.16. SD Status Register (Default Value: 0x00000006) .................................................................... 391
5.3.7.17. SD FIFO Water Level Register (Default Value: 0x000F0000) ................................................... 392
5.3.7.18. SD Function Select Register (Default Value: 0x00000000) ...................................................... 393
5.3.7.19. SD Auto Command 12 Register (Default Value: 0x0000ffff) ................................................... 394
5.3.7.20. SD NewTiming Set Register (Default Value: 0x00000001,only used in SDC1/2)..................... 394
5.3.7.21. SD Hardware Reset Register (Default Value: 0x00000001) ..................................................... 395
5.3.7.22. SD DMAC Control Register (Default Value: 0x00000000) ....................................................... 395
5.3.7.23. SD Descriptor List Base Address Register (Default Value: 0x00000000) ................................. 396
5.3.7.24. SD DMAC Status Register (Default Value: 0x0000_0000) ....................................................... 396
5.3.7.25. SD DMAC Interrupt Enable Register (Default Value: 0x00000000) ......................................... 398
5.3.7.26. Card Threshold Control Register (Default Value: 0x00000000) .............................................. 399
5.3.7.27. eMMC4.41 DDR Start Bit Detection Control Register (Default Value: 0x00000000) .............. 399
5.3.7.28. SD Response CRC Register (Default Value: 0x00000000) ........................................................ 399
5.3.7.29. SD Data7 CRC Register (Default Value: 0x00000000).............................................................. 400
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