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System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 350
4.23.2.13. PL External Interrupt Configure Register 3 (Default Value: 0x00000000)
Offset: 0x20C
Register Name: PL_EINT_CFG3
Bit
R/W
Default/Hex
Description
31:0
/
/
/
4.23.2.14. PL External Interrupt Control Register (Default Value: 0x00000000)
Offset: 0x210
Register Name: PL_EINT_CTL
Bit
R/W
Default/Hex
Description
31:12
/
/
/
[n]
(n=0~11)
R/W
0
EINT_CTL
External INTn Enable (n = 0~11)
0: Disable
1: Enable
4.23.2.15. PL External Interrupt Status Register (Default Value: 0x00000000)
Offset: 0x214
Register Name: PL_EINT_STATUS
Bit
R/W
Default/Hex
Description
31:12
/
/
/
[n]
(n=0~11)
R/W
0
EINT_STATUS
External INTn Pending Bit (n = 0~11)
0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
4.23.2.16. PL External Interrupt Debounce Register (Default Value: 0x00000000)
Offset: 0x218
Register Name: PL_EINT_DEB
Bit
R/W
Default/Hex
Description
31:7
/
/
/
6:4
R/W
0
DEB_CLK_PRE_SCALE
Debounce Clock Pre-scale n
The selected clock source is prescaled by 2^n.
3:1
/
/
/
0
R/W
0
PIO_INT_CLK_SELECT
PIO Interrupt Clock Select
0: LOSC 32KHz
1: HOSC 24MHz
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