Owners manual

Memory

Chapter 5 Memory

This section describes the H3 memory from three aspects:

 SDRAM

 NAND Flash

 SD/MMC

5.1. SDRAM

5.1.1. Overview

The SDRAM Controller (DRAMC) provides a simple, flexible, burst-optimized interface to all industy-standard SDRAM. It

supports up to a 16G bits memory address space.

The DRAMC automatically handles memory management, initialization, and refresh operations. It gives the host CPU a

simple command interface, hiding details of the required address, page, and burst handling procedures. All memory

parameters are runtime-configurable, including timing, memory setting, SDRAM type, and Extended-Mode-Register

settings. To simplify chip system integration, DDR controller works in half rate mode.

The DRAMC includes the following features:

 Support 32-bits one channel

 Support 2 Chip Select

 Support DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 SDRAM

 Support Different Memory Device’s Power Voltage of 1.2V 1.35V 1.5V and 1.8V

 Support clock frequency up to 667 MHz(DDR3-1333)

 Support Memory Capacity up to 16G bits (2G Bytes)

 Support 16 address lines and three bank address lines per channel

 Automatically generates initialization and refresh sequences

 Runtime-configurable parameters setting for application flexibility

 Priority of transferring through multiple ports is programmable

 Random read or write operation is supported

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