Owners manual

Memory

5.2. NAND Flash

5.2.1. Overview

The NDFC is the NAND Flash Controller which supports all NAND flash memory available in the market. New type flash

can be supported by software re-configuration.

The On-the-fly error correction code (ECC) is built-in NDFC for enhancing reliability. BCH is implemented and it can

detect and correct up to 64 bits error per 512 or 1024 bytes data. The on chip ECC and parity checking circuitry of NDFC

frees CPU for other tasks. The ECC function can be disabled by software.

The data can be transferred by DMA or by CPU memory-mapped IO method. The NDFC provides automatic timing

control for reading or writing external Flash. The NDFC maintains the proper relativity for CLE, CE# and ALE control

signal lines. Three modes are supported for serial read access. The conventional serial access is mode 0 and mode 1 is

for EDO type and mode 2 for extension EDO type. NDFC can monitor the status of R/B# signal line.

Block management and wear leveling management are implemented in software.

The NAND Flash Controller (NDFC) includes the following features:

 Supports all SLC/MLC/TLC flash and EF-NAND memory available in the market

 Software configure seed for randomize engine

 Software configure method for adaptability to a variety of system and memory types

 Supports 8-bit Data Bus Width

 Supports 1024, 2048, 4096, 8192, 16384 bytes size per page

 Supports Conventional and EDO serial access method for serial reading Flash

 On-the-fly BCH error correction code which correcting up to 64 bits per 512 or 1024 bytes

 Corrected Error bits number information report

 ECC automatic disable function for all 0xff data

 NDFC status information is reported by its’ registers and interrupt is supported

 One Command FIFO

 External DMA is supported for transferring data

 Two 256x32-bit RAM for Pipeline Procession

 Support SDR, ONFI DDR and Toggle DDR NAND

 Support self–debug for NDFC debug

5.2.2. Block Diagram

The NAND Flash Controller (NDFC) system block diagram is shown below:

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