Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 356
t5
t6
t15
t1
t3
t7
t8 t9
t4
t11
Addr(0) Addr(n-1)
NDFC_CLE
NDFC_CE#
NDFC_WE#
NDFC_RE#
NDFC_ALE
NDFC_IOx
Figure 5-6. Address Latch Cycle
t5
t6
t15
t1
t3
t7
t8 t9
t4
t11
D(0) D(n-1)
NDFC_CLE
NDFC_CE#
NDFC_WE#
NDFC_RE#
NDFC_ALE
NDFC_IOx
Figure 5-7. Write Data to Flash Cycle
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