Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 358
D(n-1)
05h
D(n-2)
Col1 Col2
NDFC_CLE
NDFC_CE#
NDFC_WE#
NDFC_RE
NDFC_ALE
NDFC_RB#
NDFC_IOx
t18
Figure 5-10. RE# high to WE# low Timing Diagram
Addr3
D(0)
Addr2
D(1) D(2)
NDFC_CLE
NDFC_CE#
NDFC_WE#
NDFC_RE
NDFC_ALE
NDFC_RB#
NDFC_IOx
t19
Figure 5-11. Address to Data Loading Timing Diagram
Timing cycle list:
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