Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 359
ID
Parameter
Timing
Notes
t1
NDFC_CLE setup time
2T
t2
NDFC_CLE hold time
2T
t3
NDFC_CE setup time
2T
t4
NDFC_CE hold time
2T
t5
NDFC_WE# pulse width
T
t6
NDFC_WE# hold time
T
t7
NDFC_ALE setup time
2T
t8
Data setup time
T
t9
Data hold time
T
t10
Ready to NDFC_RE# low
3T
t11
NDFC_ALE hold time
2T
t12
NDFC_RE# pulse width
T
t13
NDFC_RE# hold time
T
t14
Read cycle time
2T
t15
Write cycle time
2T
t16
NDFC_WE# high to R/B# busy
T_WB
Specified by timing configure register
(NDFC_TIMING_CFG)
t17
NDFC_WE# high to NDFC_RE# low
T_WHR
Specified by timing configure register
(NDFC_TIMING_CFG)
t18
NDFC_RE# high to NDFC_WE# low
T_RHW
Specified by timing configure register
(NDFC_TIMING_CFG)
t19
Address to Data Loading time
T_ADL
Specified by timing configure register
(NDFC_TIMING_CFG)
Notes: T is the clock period duration of NDFC_CLK (x2).
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