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Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 361
NDFC_CLE
NDFC_CE#
NDFC_WE#
NDFC_RE
NDFC_ALE
NDFC_RB#
NDFC_IOx
00h
30h
First Command
cmdio[22]
cmdio[7:0]
Address Cycle
cmdio[18:16]
cmdio[19]=1
Second Command
cmdio[24]
Wait RB Signal
cmdio[23]
Page Command
cmdio[31:30]=2
col0 col1 row0row1row2 70h d(0) 00h
Data output
Third Comand
cmdio[28]
Forth Comand
cmdio[29]
Sequence Read
cmdio[20]=0
cmdio[25]=1
Figure 5-14. EF-NAND Page Read Diagram
NDFC_CLE
NDFC_CE#
NDFC_WE#
NDFC_RE
NDFC_ALE
NDFC_RB#
NDFC_IOx
00h
30h
Data output
First Command
cmdio[22]
cmdio[7:0]
Address Cycle
cmdio[18:16]
cmdio[19]=1
Second Command
cmdio[24]
Wait RB Signal
cmdio[23]
Interleave Read
cmdio[20]=0
cmdio[25]=0
Page Command
cmdio[31:30]=2
col0 col1 row0row1row2 05h col0 col1 E0h
Data output
Address set by hardware
automatically
Figure 5-15. Interleave Page Read Diagram
5.2.5. NDFC Register List
Module Name
Base Address
NDFC
0x01C03000
Register Name
Offset
Description
NDFC_CTL
0x00
NDFC Configure and Control Register
NDFC_ST
0x04
NDFC Status Information Register
NDFC_INT
0x08
NDFC Interrupt Control Register
NDFC_TIMING_CTL
0x0C
NDFC Timing Control Register
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