Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 362
NDFC_TIMING_CFG
0x10
NDFC Timing Configure Register
NDFC_ADDR_LOW
0x14
NDFC Low Word Address Register
NDFC_ADDR_HIGH
0x18
NDFC High Word Address Register
NDFC_BLOCK_NUM
0x1C
NDFC Data Block Number Register
NDFC_CNT
0x20
NDFC Data Counter for data transfer Register
NDFC_CMD
0x24
Set up NDFC commands Register
NDFC_RCMD_SET
0x28
Read Command Set Register for vendor’s NAND memory
NDFC_WCMD_SET
0x2C
Write Command Set Register for vendor’s NAND memory
NDFC_ECC_CTL
0x34
ECC Configure and Control Register
NDFC_ECC_ST
0x38
ECC Status and Operation information Register
NDFC_EFR
0x3C
Enhanced Feature Register
NDFC_ERR_CNT0
0x40
Corrected Error Bit Counter Register 0
NDFC_ERR_CNT1
0x44
Corrected Error Bit Counter Register 1
NDFC_USER_DATAn
0x50+4*n
User Data Field Register n (n from 0 to 15)
NDFC_EFNAND_STA
0x90
EFNAND Status Register
NDFC_SPARE_AREA
0xA0
Spare Area Configure Register
NDFC_PAT_ID
0xA4
Pattern ID Register
NDFC_RDATA_STA_CTL
0xA8
Read Data Status Control Register
NDFC_RDATA_STA_0
0xAC
Read Data Status Register 0
NDFC_RDATA_STA_1
0xB0
Read Data Status Register 1
NDFC_MDMA_ADDR
0xC0
MBUS DMA Address Register
NDFC_MDMA_CNT
0xC4
MBUS DMA Data Counter Register
NDFC_IO_DATA
0x300
Data Input/ Output Port Address Register
RAM0_BASE
0x400
1024 Bytes RAM0 base
RAM1_BASE
0x800
1024 Bytes RAM1 base
5.2.6. NDFC Register Description
5.2.6.1. NDFC Control Register(Default Value: 0x00000000)
Offset: 0x00
Register Name: NDFC_CTL
Bit
R/W
Default/Hex
Description
31:28
/
/
/
27:24
R/W
0
NDFC_CE_SEL
Chip Select for 8 NAND Flash Chips
0 -7: NDFC Chip Select Signal 0-7 is selected
8-15: NDFC CS[7:0] not selected. GPIO pins can be used for CS. NDFC can
support up to 16 CS.
23:22
/
/
/
21
R/W
0
NDFC_DDR_RM
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