Owners manual

Memory
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 363
DDR Repeat data mode
0: Lower byte
1: Higher byte
20
R/W
0
NDFC_DDR_REN
DDR Repeat Enable
0: Disable
1: Enable
19:18
R/W
0
NF_TYPE
NAND Flash Type
0x0: Normal SDR NAND
0x1: Reserved
0x2: ONFI DDR NAND
0x3: Toggle DDR NAND
17
R/W
0
NDFC_CLE_POL
NDFC Command Latch Enable (CLE) Signal Polarity Select
0: High active
1: Low active
16
R/W
0
NDFC_ALE_POL
NDFC Address Latch Enable (ALE) Signal Polarity Select
0: High active
1: Low active
15
R/W
0
NDFC_DMA_TYPE
0: Dedicated DMA
1: Normal DMA
14
R/W
0
NDFC_RAM_METHOD
Access internal RAM method
0: Access internal RAM by AHB bus
1: Access internal RAM by DMA bus
13:12
/
/
/
11:8
R/W
0x0
NDFC_PAGE_SIZE
0x0: 1024 bytes
0x1: 2048 bytes
0x2: 4096 bytes
0x3: 8192 bytes
0x4: 16384 bytes
Notes: The page size is for main field data.
7
/
/
/
6
R/W
0
NDFC_CE_ACT
Chip Select Signal CE# Control During NAND operation
0: De-active Chip Select Signal NDFC_CE# during data loading, serial access
and other no operation stage for power consumption. NDFC automatic
control Chip Select Signals.
1: Chip select signal NDFC_CE# is always active after NDFC is enabled
5
/
/
/
4:3
R/W
0
NDFC_RB_SEL
confidential