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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 364
NDFC external R/B Signal select
The value 0-3 selects the external R/B signal. The same R/B signal can be
used for multiple chip select flash.
2
R/W
0
NDFC_BUS_WIDTH
0: 8-bit bus
1: 16-bit bus
1
R/W
0
NDFC_RESET
NDFC Reset
Write 1 to reset NDFC and clear to 0 after reset
0
R/W
0
NDFC_EN
NDFC Enable Control
0: Disable NDFC
1: Enable NDFC
5.2.6.2. NDFC Status Register(Default Value: 0x00000000)
Offset: 0x04
Register Name: NDFC_ST
Bit
R/W
Default/Hex
Description
31:14
/
/
/
13
R
/
NDFC_RDATA_STA_0
0: The number of bit 1 during current read operation is greater threshold
value.
1: The number of bit 1 during current read operation is less than or equal to
threshold value.
This field only is valid when NDFC_RDATA_STA_EN is 1.
The threshold value is configured in NDFC_RDATA_STA_TH.
12
R
/
NDFC_RDATA_STA_1
0: The number of bit 0 during current read operation is greater threshold
value.
1: The number of bit 0 during current read operation is less than or equal to
than threshold value.
This field only is valid when NDFC_RDATA_STA_EN is 1.
The threshold value is configured in NDFC_RDATA_STA_TH.
11
R
/
NDFC_RB_STATE3
NAND Flash R/B 3 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State
10
R
/
NDFC_RB_STATE2
NAND Flash R/B 2 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State
9
R
/
NDFC_RB_STATE1
NAND Flash R/B 1 Line State
0: NAND Flash in BUSY State
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